More M571 power supply notes
(1) The CPU I/O voltage regulator
The adjustable linear voltage regulator (H1085) is able to supply a
maximum of 3 Amps to the RAM and to the CPU. For dual voltage CPUs
(P55C), this regulator supplies the I/O voltage.
Here is the relevant circuit:
                              |--o CPU I/O jumper JP8-1
      in |-------| out        |--o to cache RAM
 +5V o---| H1085 |---|--------|--o to SDRAM voltage jumper JP4
         |---|---|   |
         adj |      |-|
             |      | | 120 ohm
             |      |-| R56
                    | | 215 ohm
The output voltage is actually 3.49V, not 3.3V. (I measured 3.46V)
The relevant formula is:
  Vout = 1.25 (1 + 215/120)
(2) The core voltage regulator
This is a switching power supply consisting of a PWM control IC
(KA7500B), a TrenchMOS FET chopper (Q9), a diode (Q8), and an LC circuit
comprising inductor L20 and capacitors EC27, EC32, and EC24.
My reservation about this circuit is that the capacitors are standard
types (G-Luxon 105 deg SM series). The LM or HM types have much lower
ESR (equivalent series resistance) and would be better choices for this
switchmode power supply.
Here is a rough circuit diagram:
            ferrite                       L20
            beads             FET         coil
             L18             |---|        =====        to JP8
  +5V o--|--[]-[]--|---------|Q9 |----|---/\/\/---|--o core jumper
       +_|_      +_|_        |-|-|   _|_        +_|_       
  EC18  ___       ___ EC22     |     / \  Q8     ___ EC27
  EC35   | 4000uF  |  1500uF   |    /-|-\ diode   |  EC32 3500uF
  EC36  _|_       _|_          |     _|_         _|_ EC24
  EC21   =         =        ___|___   =           =
                           |       |
(3) Block diagram
        |------------| 3.49V          |--o to SDRAM voltage JP4
 +5V o--| I/O V Reg  |--------|-------|--o to cache RAM
        |------------|        |
                             | |
                           1 O O P55C (dual voltage)
                      JP8  2 O-O---------o to CPU I/O
                      A&B  3 O O P54C (single voltage)
        |------------|        |
 +5V o--| Core V Reg |--------|----------o to CPU core
Note that jumpers JP8-A and JP8-B must be in identical positions, ie
both in the 1-2 position or both in the 2-3 position. Any other scheme
causes both regulator outputs to be connected together. I cannot predict
the result of such an error, but I believe damage is possible.
Note also that the manual stipulates that, in single voltage mode the
core voltage must be set to the 3.5V position, ie the highest setting.
(4) How to measure the CPU core and I/O voltages.
With CPU installed, the core voltage regulator output is measured at JP8
pin 3. The I/O voltage regulator output is found at JP8-1.
If experimenting with undocumented voltages, and in the absence of a
CPU, remove the JP8 jumpers and connect a 2.2 ohm, 10Watt resistor
(~1-1.5 amp dummy load) between JP8-3 and a suitable ground, eg pin 3 of
the fan power connector JP2.
Take care. The resistor will get hot.
                             | |
                           1 O O
                      JP8  2 O O      ____      fan power ground
                      A&B  3 O O-----|____|---O J2-3
                             |_|     2.2ohm
                              |      10 Watt
        |------------|        |      resistor
 +5V o--| Core V Reg |--------|

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 This page was last modified on 17 July 2002