Motherboard manufacturers must write BIOS code to match any configuration that their customers might use. It is possible to configure your M571 3.2, 3.2a, or 7.0 BIOS settings in such a way that normal compromises are minimized and performance is maximized.
Not necessarily. CMOS settings should be optimized for best performance, but they do not provide access to all of the settings that may optimize your upgraded M571. Generally, the 04-21-99 BIOS release (can be downloaded from this site) provides a good beginning: bug problems are minimized and HDD support for up to 32 GB disks is reliable. "Write Allocation" and "Write Combining" features of the AMD K6 2 and K6 3 CXT core chips are enabled in the 04-21-99 BIOS release. (This is often not the case for BIOS releases of other motherboards.)
Any of the modifications described on these pages are dangerous if implemented by someone who does not use good common sense and craftsmanship. Those who refuse to follow directions and jump at various points while disregarding an understanding of their project's "big picture" are bound to get into trouble. The same is true of tweaking chipset BIOS settings.
But, if you are methodical and careful, and if you posses a normal amount of understanding and common sense, you may be able to realize a useful performance increase from your M571. I take no responsibility for your results, good or bad: this page simply outlines what has worked for others and myself. If you try this, the risk is entirely your own!
The process explained here assumes you have modified your system with an AMD K6 2 or K6 3 processor, have PC100 DIMMs installed, and that your system is operating reliably, although this information may prove useful if your system is not using these processors.
I tested my system with Sandra
2001te, a benchmarking program that can be downloaded and used for this purpose
free of charge. I originally started testing with Sandra 2001se. The 2001te
version is more stable, but does give different CPU and Multimedia benchmarks.
Memory benchmarks were similar between the two versions, however.
|
|
CPU perf. |
Perf. Rating |
Multimedia |
Memory perf. |
|
Before tweaking |
1103/558 |
550 |
1492/1951 |
109/116 |
|
After tweaking |
1103/558 |
550 |
1493/1951 |
124/134 |
CPU performance is unchanged, but the memory performance is improved about 15%.
The setup of the system is described here: timmy's M571
These methods will work with Win9x or W2K operating systems.
This task is explained in two sections. First, the bare essentials needed to duplicate the settings that I've used to achieve my results are presented, along with how to implement them. Note that I DO NOT recommend that you simply install a copy of my settings without testing whether they really work.
Secondly, what changes have been made are described, along with an explanation of how one could use available resources to optimize their own settings.
You will need an application that loads the register settings when Windows loads. wpcrset is an application that loads with Windows. It can be bypassed by starting in Safe Mode, corrected, and then rebooted if you make an entry that is unsuccessful. Download wpcrset
Use Sandra 2001 to measure whether each modification you make to chipset settings increases memory performance. Download Sandra 2001 from http://www.sisoftware.co.uk/sandra.
Finally, have a piece of paper and a pencil ready to record exactly what you have done. This step is actually the most important one, so don't neglect it!
After downloading the two applications and installing them on your system, you are ready to begin.
First, reboot your machine, and without running any other programs, open Sandra 2001. Run the Memory benchmark, the CPU Multimedia benchmark, and the CPU benchmark. Run each test in the same order. You won't need to repeat the CPU Multimedia benchmark, and the CPU benchmark until you are satisfied with your memory testing results.
RECORD YOUR RESULTS.
Now reboot your system and run the benchmarks again, and then do so a third time. Compare your results. They should be very close, indicating you have a reliable measurement. If you have moved your mouse or bumped the system while a test is running, it can falsify the results of that test.
Open wpcrset. Click the "ADD" button. Do not make any entries in the left hand three boxes. Their values should be "0", "0", and "0" for Bus, Device, and function. We are modifying the Host to PCI bridge, which is represented by these values. In the right hand two boxes, enter 52 in the register box and E0 in the data box. Make sure you have entered this information EXACTLY as it is written here. Record the information on your notes. Click the "OK" button and click the main application "OK" button to exit wpcrset. When you do this, the application will ask if you want to reboot your system now, and you should choose to reboot.
When your system has rebooted, go directly to Sandra 2001 without opening any other programs, and run the Memory Benchmark to see if your change has made a difference in your measurements. If no difference has been made or memory performance is less, restart your system and measure your memory performance again. If there still is no change or a lesser figure than your baseline, open wpcrset and remove the 52 register entry from the application menu.
If you have effected a performance increase, do not delete the entry.
At this point, enter the memory benchmark figure you obtained in your notes, and proceed to add another entry in wpcrset. Click the "ADD" button and enter 54 in the register field and 03 in the data field. CLICK 2 "OKs" as before and restart your system. Run Sandra 2001 again and note your results.
At this point, those of you who couldn't wait to try this either have obtained a performance increase, or you haven't, and the more careful of you want to know exactly what this modification does before you are willing to consider doing it.
The most important tool you will need at this point is a technical description of how the SiS 5597/5598 chipset works. This document contains register descriptions and setting values, which is what the tweaking process modifies. The technical document can be downloaded from SiS's website by clicking here: 5597/5598 datasheet
I'd like to digress here for a minute and urge you to download this datasheet. It is now a Wordpad .doc file, and it's not easy to use. The link is no longer posted and downloading large files from Taiwan sites is challenging. This datasheet used to be available in Adobe Acrobat .pdf format, much easier to use but four times larger. These documents are getting harder to find as the products become obsolete, so download them now, while they are still available!
The section titled "Register Description" describes all of the registers in the 5597/5598 chipset and what permissible values enable various features. By reading this document, you will know what Hex address (e.g., "54h") to enter in the register box of wpcrset.
The application wpcredit is a good way to see how registers are currently set in M571 chipsets. It also available from ftp://ftp.vector.co.jp/pack/win95/hardware/other/wpcre12a.exe. Download this application and install it on your system. When wpcredit is opened, the Hex address "10s" column is shown down the side, and the "units" values are shown across the top. Each entry represents the setting of eight bits in Hex notation. By moving the cursor around the screen, a box at center bottom will display the hex and equivalent binary value of each chipset register.
Other chipset functions, Such as the PCI to ISA bridge and the video function in the chipset can be modified by placing other values in the function and device boxes of wpcrset. Descriptions of these registers are also contained in the datasheet, and their values can be viewed in wpcredit by clicking on the "select device" button in the toolbar.
Hex is used as a convenient way to record binary settings. These instructions assume that you have some familiarity with hex. As a reminder, note that a register of eight bits is represented by two hexidecimal digits. For example, say the hexidecimal digits are "95". The first hexidecimal digit represents the "most significant bits" or bits 7 through 4. The second hex digit represents the "least significant bits", or bits 3 through 0. "9" in hex would be "1001", or 1 "eight", 0 "four", 0 "two" and 1 "unit" and "5" in hex represents 0101 in binary, or 0 "eight", 1 "four", 0 "two" and 1 "unit". Therefor, the whole register is "95" in hex and 10010101 in binary. The hex representation of register values is what is seen in the wpcredit application.
If this sounds like gibberish, there is a handy tool in Windows for this conversion. Open the calculator and under "view", select "scientific". Click the "hex" button and enter the rester value, and then click the "bin" (or binary) button. the register value will be displayed, starting with bit 7 on the left and continuing to bit 0 on the right. It is important to remember that all leading zeros are not reported, so a word of 00101011 would simply appear on the calculator as 101011. Remember this, or it could cause problems!
Here are two examples that will help you use the datasheet to make tweak decisions.
First, recall that I suggested changing register 52h in the opening section of this page. Turning to the Register Description section of the Datasheet, here is the description of that Register:
Register 52h Control Register (default = 00h)
Bit 7 CPU L1 Cache Write Back Mode Enable
0: Disable
1: Enable
Bit 6 Single read Allocation (L2 update) Control
0: Disable
1: Enable
Bit 5 Read FIFO Control
0: Disable
1: Enable
Bit 4 Reserved
Bit 3 Reserved
This bit should be programmed to 0.
Bit 2 Reserved
This bit is programmed to 0.
Bit 1 DRAM Refresh Mode (internal use only)
0: Normal Mode
1: Test Mode
Bit 0 Internal SRAM test mode (internal use only)
0: Normal Mode
1: Test Mode
Note: I'm not going to enter into an explanation of how to use hex at this point, except to note that hex is counted in this manner: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, 10. This will help you to find the Registers in the datasheet
Open wpcredit and move the cursor down the left column to "50", then move the cursor right under the "2" column. You will see that the value of Register 52 is "C0". At the center bottom box of wpcredit, note that "C0" = binary 11000000. I wanted to enable FIFO control, so I changed bit 5 from a "0" to a "1". The value of Register 52h then becomes to "E0", which is put in the "data" box of wpcrset. Setting the FIFO bit to "1" enables Read FIFO control, according to the datasheet.
When you "OK" out of wpcrset and restart your system, you will see that the value is changed in wpcredit to "E0".
This can be done, but if the system is tested with Sandra 2001 without a restart, memory readings won't be the same as after a fresh restart. To truly understand if your change has made a difference and to quantify that difference, you must run Sandra the same way after each change. That's why I recommend using wpcrset and restarting the system after each change. Also, the changes made in wpcredit don't remain after a system is restarted. In essence, I'm recommending the use of wpcredit just to view the present values of registers, not to change them.
I also suggested changing Register 54h. Here is the description of 54h from the datasheet:
Register 54h DRAM Control Register 0(default = 54h)
Bits 7:6 RAS pulse width when refresh Cycle
00: 5T for EDO/FP DRAM and 4T for SDRAM
01: 6T for EDO/FP DRAM and 5T for SDRAM
10: 7T for EDO/FP DRAM and 6T for SDRAM
11: 8T for EDO/FP DRAM and 7T for SDRAM
Bits 5:4 RAS precharge time
00: 2T
01: 3T
10: 4T
11: 5T
Bits 3:2 RAS to CAS delay
00: 2T
01: 3T
10: 4T
11: 5T
Bit 1 CAS pulse width only for FPM DRAM
0: 2T
1: 1T
Bit 0 CAS pulse width only for EDO DRAM
0: 2T
1: 1T
The old value for this register was 95. Note that, according to the data sheet, 95, (or 10010101) set a pulse width of 6T for SDRAM. this means that the pulse is 6 clock "ticks" wide. The second two values were set to three "ticks". The last two bits set CAS pulse widths that don't apply to SDRAM. I changed the value of 54h to 03 hex, or 00000011, which set all of these values to the minimum time. This means that the system will wait fewer "ticks" for each of these tasks to be performed.
NO! This page provides the names of applications and documents, and also their locations. It also gives a brief overview of how to go through the process of reading the chipset datasheet and making the changes that YOU think are necessary. Making the wrong changes to chipset register settings can have damaging consequences for your chipset and system. This information tells how to do it. It is your decision to try and improve your system's performance and what changes to make, and it is your risk to assume.
If you modify a register and, upon rebooting, find that your system locks up or exhibits other undesirable traits, shut the system down and restart in Safe Mode. Start wpcrset in Safe Mode and remove the last register tweak you entered, and then restart the system normally. This is one reason why it is good practice to make one change at a time!
After entering wpcrset, one can also check the option to not load the application on startup, then restart the system normally, nullifying all settings.
Register 50h, Host Interface and DRAM arbiter, bit 6 must be set to "disable" with an AMD processor, since write allocation is enabled. This is referred to as L2 cache dirty tag by some sources.
Register 53h, DRAM Control Register, bits 4 and 3 are usually set to enable page misses after data and code read DRAM cycles. Disabling these functions caused a drop in performance. (See section below; on my system more performance was gained by having all 3 page miss registers enabled.)
Register 53h, DRAM Control Register, bits 2 and 1 caused my system to lock when I set the refresh cycle time value to 00, or 15.6us. (This value can be set in CMOS under Advanced Chipset Setup, Refresh Cycle Time. 15.6us corresponds to a "0" setting in CMOS. My system uses a "4", or 62.4us setting in CMOS. I have accessed all my registers though CMOS where possible.)
Register 56h, bits 5, 4, SDRAM Read Cycle Lead-off Time: this register was normally set to 00, or normal timing. Changing these bits to 01, or faster timing, eliminates one "tick" from the read cycle lead off time. The faster timing had variable results, but usually lower than the best performance obtained when the setting was normal. Also, CPU performance was often slower.
Register 56h, MDLE Delay Control Register, bits 2, 1, 0: The original setting was 011, or a 3ns delay. I found no improvement at 2ns or 1ns.
Register 57h, SDRAM Control Register, bit 4 controls CAS Latency. This is usually set to 3T, and it can only be changed to 2T if the system has CAS 2 DIMMs. This setting must be made at boot up. (CAS 2 memory will improve performance over CAS 3. I intend to acquire 2 128 MB CAS 2 DIMMs in the future. Note that not all 128 MB DIMMs can be used on M571 systems and that only 128 MB of RAM is cached by the onboard L2 cache. Only the use of a K6 3 processor, with L2 cache present on the chip, can cache 256 MB of memory.)
Register 80h, bits 7, 6, 5, PCI Burstable Length Selection: no improvement when increased from 010, 1 KB length, to 2 KB.
Register 81h: Note that bits 7 and 6 depend system Front Side Bus Speed. Mine is running at 83.3 MHz, so these values were left at the slower settings recommended by the datasheet. I did set bit 3, burst read, to "enable", but bit 2, concurrency mode, must be left to "disable" on my system.
Register 82h: I left bit 6, PEADS timing, to "slower", since I'm running 83.3 MHz Front Side Bus rate.
These are some examples of my work on my system's chipset register values. I am trying other combinations. This information demonstrates that useful performance increases can be obtained by careful and methodical trial and error methods. However, it is necessary to inform one's self with the datasheet and have a reasonable idea of what may work and what may not.
At this point, here are my
present tweaks:
|
Hex Address |
Old Setting |
New Setting |
Bit |
Modification |
|
52h |
C0 |
E0 |
5 |
Enable Read FIFO Control |
|
53h |
1A |
3A |
5 |
Enable page miss after DRAM write |
|
54h |
95 |
03 |
7,6 |
Reduce RAS refresh pulse width from 6T to 4T |
|
" |
" |
" |
5,4 |
Reduce RAS precharge from 3T to 2T |
|
" |
" |
" |
3,2 |
Reduce RAS to CAS delay from 3T to 2T |
|
" |
" |
" |
1 |
Reduce CAS pulse width from 2T to 1T |
|
55h |
34 |
80 |
7 |
Reduce assertion timing from 3T to 2T |
|
" |
" |
" |
5 |
Disable read cycle delay after write |
|
" |
" |
" |
4,3 |
Reduce CAS precharge from 2T to 1T |
|
" |
" |
" |
2,1 |
Reduce CAS precharge from 2T to 1T |
|
80h |
5A |
5E |
2 |
Enable advanced snoop in PCI master read cycle |
|
81h |
C0 |
C8 |
3 |
Enable Synchronous DRAM burst read |
|
83h |
FD |
FF |
1 |
Enable CPU to PCI burst memory write |
I hesitated to put this page up on the site. It is inevitable that someone will try it and come to grief over their results. My feeling on this is that those who take the time and effort to study available material and pursue a common sense approach to tweaking ought not to have information withheld from them to protect those who might not perform the job correctly.
I must repeat the stress on care and craftsmanship if you choose to try your hand at chipset tweaking, and wish you the best of results.
This page was last modified on 13 July 2002